Author:
Jindal Poonam,Kaushik Aryan,Kumar Keshav
Cited by
12 articles.
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1. SSTL IO Standard Based Low Power Design of DES Encryption Algorithm on 28 nm FPGA;2024 IEEE 13th International Conference on Communication Systems and Network Technologies (CSNT);2024-04-06
2. Comparative Analysis of Hardware and Software Utilization in the Implementation of Full Adder Using Vivado;2023 7th International Conference On Computing, Communication, Control And Automation (ICCUBEA);2023-08-18
3. Verilog Implementation and Functional Verification of Hybrid Cryptography Algorithm;2023 14th International Conference on Computing Communication and Networking Technologies (ICCCNT);2023-07-06
4. Comparative Analysis of Power and Hardware Utilization in an Energy-Efficient 8:3 Encoder;2023 4th International Conference on Electronics and Sustainable Communication Systems (ICESC);2023-07-06
5. Implementation of an Energy Efficient Flip Flop by using Kintex, Virtex and Genesys FPGA Families;2023 International Conference on Sustainable Computing and Data Communication Systems (ICSCDS);2023-03-23