Implementation of an Energy Efficient Flip Flop by using Kintex, Virtex and Genesys FPGA Families
Author:
Affiliation:
1. Chitkara University Institute of Engineering and technology Chitkara University,Punjab,India
2. Maharishi Markandeshwar (Deemed to be University),Dept. of CSE, MM Engg college,Mullana,Haryana,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10104520/10104522/10104999.pdf?arnumber=10104999
Reference16 articles.
1. Utilizing manufacturing variations to design a tri-state flip-flop PUF for IoT security applications
2. Design and implementation of basic building blocks of FPGA using memristor-transistor hybrid approach
3. Implementation of Verilog HDL in Calculator Design with FPGA Simulation
4. FPGA implementation of image enhancement algorithms
5. A Methodology to Emulate Single Event Upsets in Flip-Flops Using FPGAs through Partial Reconfiguration and Instrumentation
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