Systolic Array Based Convolutional Neural Network Inference on FPGA-Reference-Cited by-同舟云学术

Systolic Array Based Convolutional Neural Network Inference on FPGA

Published:2022-12 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE 15th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)
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Author:

Chua Shi Hui¹,Teo T. Hui²,Tiruye Mulat Ayinet¹,Wey I-Chyn³

Affiliation:

1. Singapore University of Technology and Design,Engineering Product Development,Singapore

2. Singapore University of Technology and Design,Engineering Product Development, Science Mathematics and Technology,Singapore

3. Artificial Intelligence Research Center, School of Electrical and Computer Engineering College of Engineering, Graduate Institute of Electrical Engineering, Chang Gung University, Chang Gung University,Taiwan

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10008388/10008225/10008429.pdf?arnumber=10008429

Reference11 articles.

1. Impact of the Array Shape and Memory Bandwidth on the Execution Time of CNN Systolic Arrays

2. High-performance Convolutional Neural Network Accelerator Based on Systolic Arrays and Quantization

3. Implementation of Binarized Neural Networks in All-Programmable System-on-Chip Platforms

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3. Systolic Array Architecture for Educational Use;2023 27th International Conference on System Theory, Control and Computing (ICSTCC);2023-10-11

4. A-DSCNN: Depthwise Separable Convolutional Neural Network Inference Chip Design Using an Approximate Multiplier;Chips;2023-07-19