A junction temperature prediction model for 3D stacked packaging chip based on thermal resistance matrix-Reference-Cited by-同舟云学术

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A junction temperature prediction model for 3D stacked packaging chip based on thermal resistance matrix

Published:2023-08-08 Issue: Volume: Page:1-5
ISSN:
Container-title:2023 24th International Conference on Electronic Packaging Technology (ICEPT)
language:
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Author:

Liu Jiahao¹,Chen Fangzhou¹,Zhao Hao¹,Xiao Hui¹,Diao He²,Zhong Xiangxiang²,Wang Fengyi²,Liu Hao³,Guo Xiaotong⁴

Affiliation:

1. China Electronic Product Reliability and Environmental Testing Research Institute,Guangzhou,China,511370

2. Harbin Institute of Technology,Department of Materials Science and Engineering,Shenzhen,China,518055

3. Beijing Santel Technology & Trading Corp.,Beijing,China,100854

4. Chongqing CEPREI Industrial Technology Research Institute Co., Ltd,Chongqing,China,401332

Funder

Research and Development

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10491594/10491891/10492176.pdf?arnumber=10492176

Reference8 articles.

1. Thermal characterization of TSV based 3D stacked ICs

2. Thermal characterization of stacked-die packages

3. Thermal management of 3D stacked dies with air convection and water cooling methods

4. Thermal Measurement and Modeling of Multi-Die Packages

5. Measurement and simulation of stacked die thermal resistances

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