Thermal characterization of TSV based 3D stacked ICs
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/6424014/6457827/06457910.pdf?arnumber=6457910
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Thermal Modeling and Analysis of 3D ICS with Heat Dissipation Effect of Power Distribution Networks;Journal of Circuits, Systems and Computers;2024-07-20
2. A junction temperature prediction model for 3D stacked packaging chip based on thermal resistance matrix;2023 24th International Conference on Electronic Packaging Technology (ICEPT);2023-08-08
3. Research on Flip-Chip Bonding Process and Thermal Cycle Reliability Simulation of 3-D Stacked Structure;IEEE Transactions on Components, Packaging and Manufacturing Technology;2022-01
4. Quasi-3D Thermal Simulation of Integrated Circuit Systems in Packages;Energies;2020-06-12
5. Extending BookSim2.0 and HotSpot6.0 for power, performance and thermal evaluation of 3D NoC architectures;Simulation Modelling Practice and Theory;2019-11
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