A 1-Tb 4-b/cell 4-Plane 162-Layer 3-D Flash Memory With 2.4-Gb/s IO Interface

Author:

Yuh Jong Hak1ORCID,Li Yen-Lung Jason1,Li Heguang1,Oyama Yoshihiro1,Hsu Cynthia1,Anantula Pradeep1,Jeong Gwang Yeong Stanley1,Amarnath Anirudh1,Darne Siddhesh1,Bhatia Sneha1,Tang Tianyu1,Arya Aditya1,Rastogi Naman1,Ookuma Naoki1,Mizukoshi Hiroyuki1,Yap Alex1,Wang Demin1,Kim Steve1,Wu Yonggang1,Peng Min1,Lu Jason1,Ip Tommy1,Malhotra Seema1,Han Taekeun1,Okumura Masatoshi1,Liu Jiwen1ORCID,Sohn Jeongduk John1,Chibvongodze Hardwell1,Balaga Muralikrishna1,Matsuda Akihiro1,Chen Chen1ORCID,K. V. Indra1,G. V. S. N. K. Chaitanya1,Ramachandra Venky1,Kato Yosuke1,Kumar Ravi J.1,Wang Huijuan1,Moogat Farookh1,Yoon In-Soo1,Kanda Kazushige2,Shimizu Takahiro2,Shibata Noboru2,Yanagidaira Kosuke2,Kodama Takuyo2,Fukuda Ryo2,Hirashima Yasuhiro2,Abe Mitsuhiro2

Affiliation:

1. Western Digital, Milpitas, CA, USA

2. KIOXIA Corporation, Yokohama, Japan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Reference18 articles.

1. 13.2 A 1Tb 4b/Cell 96-Stacked-WL 3D NAND Flash Memory with 30MB/s Program Throughput Using Peripheral Circuit Under Memory Cell Array Technique

2. 30.2 A 1Tb 4b/cell 144-tier floating-gate 3D-NAND flash memory with 40MB/s program throughput and 13.8Gb/mm2 bit density;khakifirooz;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2021

3. 13.1 A 1.33Tb 4-bit/cell 3D-flash memory on a 96-word-line-layer technology;shibata;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2019

4. A 1Tb 4b/cell NAND flash memory with $\text{t}_{\textrm{PROG}}$ =2ms, $\text{t}_{\textrm{R}}$ =$110~\mu\text{s}$ and 1.2Gb/s high-speed IO rate;kim;IEEE ISSCC Dig Tech Papers,2020

5. 13.1 A 1.33Tb 4-bit/cell 3D-flash memory on a 96-word-line-layer technology;shibata;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2019

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