A 7-nm FinFET 1.2-TB/s/mm$^{2}$ 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver
Author:
Affiliation:
1. Graduate School of Engineering, The University of Tokyo, Tokyo, Japan
2. Research Association for Advanced Systems (RaaS), Tokyo, Japan
Funder
JST ACT-X
JSPS KAKENHI
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/4/4359912/09968287.pdf?arnumber=9968287
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A novel high-performance TG-based SRAM cell with 5 nm FinFET technology;Engineering Research Express;2024-06-01
2. A Cross-Process Signal Integrity Analysis (CPSIA) Method and Design Optimization for Wafer-on-Wafer Stacked DRAM;Micromachines;2024-04-23
3. Design of a new serial control and detection module based on Manchester encoding;International Conference on Optoelectronic Materials and Devices (ICOMD 2023);2024-02-08
4. At the Locus of Performance: Quantifying the Effects of Copious 3D-Stacked Cache on HPC Workloads;ACM Transactions on Architecture and Code Optimization;2023-12-14
5. Polyomino: A 3D-SRAM-Centric Accelerator for Randomly Pruned Matrix Multiplication With Simple Reordering Algorithm and Efficient Compression Format in 180-nm CMOS;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-09
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