A Self-Calibrated 2-bit Time-Period Comparator-Based Synthesized Fractional-N MDLL in 22-nm FinFET CMOS-Reference-Cited by-同舟云学术

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A Self-Calibrated 2-bit Time-Period Comparator-Based Synthesized Fractional-N MDLL in 22-nm FinFET CMOS

Published:2021-01 Issue:1 Volume:56 Page:43-54
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Kundu Somnath^ORCID,Chai Likai,Chandrashekar Kailash,Pellerano Stefano,Carlton Brent R.^ORCID

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/9306027/09195732.pdf?arnumber=9195732

Cited by 19 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 6 to 12-GHz Fractional-N Frequency Synthesizer With a Digital Technique to Counter Modulus-Dependent Feedback Divider Delays;IEEE Journal of Solid-State Circuits;2024-09

2. A 12.24-GHz MDLL With a 102-Multiplication Factor Using a Power-Gating-Based Ring Oscillator;IEEE Journal of Solid-State Circuits;2024

3. Fractional-N Digital MDLL With Injection-Error Scrambling and Calibration;IEEE Journal of Solid-State Circuits;2024-01

4. A Fully Synthesizable Fractional-N MDLL With Energy-Efficient Ring-Oscillator-Based DTC of Large Tuning Range;IEEE Solid-State Circuits Letters;2024

5. Design of Synthesizable Digital Phase Locked Loops;IPSJ Transactions on System and LSI Design Methodology;2024

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