Performance Investigation Of Extended Vertical Double Gate Tunnel Field Effect Transistor
Author:
Affiliation:
1. National Institute of Technology,Department of Electronics and Communication Engineering,Delhi,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9751451/9751452/09751635.pdf?arnumber=9751635
Reference18 articles.
1. Optimization of L-shaped tunneling field-effect transistor for ambipolar current suppression and Analog/RF performance enhancement
2. Analog/RF Performance of T-Shape Gate Dual-Source Tunnel Field-Effect Transistor
3. Vertical P-TFET With a P-Type SiGe Pocket
4. Band Engineering to Improve Average Subthreshold Swing by Suppressing Low Electric Field Band-to-Band Tunneling With Epitaxial Tunnel Layer Tunnel FET Structure
5. p-Channel TFET Operation of Bilayer Structures With Type-II Heterotunneling Junction of Oxide- and Group-IV Semiconductors
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1. Investigation of the Electrical Parameters in a Partially Extended Ge-Source Double-Gate Tunnel Field-Effect Transistor (DG-TFET);Journal of Electronic Materials;2024-03-26
2. Linearity Analysis of Charge Plasma-Induced Graded Channel Nanotube at Varying Temperatures;2023 International Conference on Self Sustainable Artificial Intelligence Systems (ICSSAS);2023-10-18
3. Investigation of Temperature Variation in Partially Extended Si1-xGex Source Double Gate Tunnel FET;2022 IEEE 3rd Global Conference for Advancement in Technology (GCAT);2022-10-07
4. Partially Extended Germanium Source DG-TFET: Design, Analysis, and Optimization for Enhanced Digital and Analog/RF Parameters;Silicon;2022-09-21
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