Interconnect architecture exploration for low-energy reconfigurable single-chip DSPs-Reference-Cited by-同舟云学术

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Interconnect architecture exploration for low-energy reconfigurable single-chip DSPs

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Container-title:Proceedings. IEEE Computer Society Workshop on VLSI '99. System Design: Towards System-on-a-Chip Paradigm
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Author:

Hui Zhang ,Marlene Wan ,George V.,Rabaey J.

Publisher

IEEE Comput. Soc

Link

http://xplorestaging.ieee.org/ielx4/6154/16456/00760456.pdf?arnumber=760456

Cited by 16 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Double Pumping Low Power Technique for Coarse - Grained Reconfigurable Architecture;International Journal of Electrical and Electronics Research;2016-03-31

2. Processor Tile Shapes and Interconnect Topologies for Dense On-Chip Networks;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2014-06

3. POWER-EFFICIENT CONFIGURATION CACHE STRUCTURE FOR COARSE-GRAINED RECONFIGURABLE ARCHITECTURE;Journal of Circuits, Systems and Computers;2013-03

4. Dynamic Context Compression for Low-Power CGRA;Design of Low-Power Coarse-Grained Reconfigurable Architectures;2010-12-09

5. Power‐Aware Multicore SoC and NoC Design;Multiprocessor System-on-Chip;2010-11-09

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