A 6.5-to-8GHz Cascaded Dual-Fractional-N Digital PLL Achieving -63.7dBc Fractional Spurs with 50MHz Reference-Reference-Cited by-同舟云学术

A 6.5-to-8GHz Cascaded Dual-Fractional-N Digital PLL Achieving -63.7dBc Fractional Spurs with 50MHz Reference

Published:2023-04 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE Custom Integrated Circuits Conference (CICC)
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Author:

Xu Dingxin¹,Zhang Yuncheng¹,Huang Hongye¹,Sun Zheng¹,Liu Bangan¹,Fadila Ashbir Aviat¹,Qiu Junjun¹,Liu Zezheng¹,Wang Wenqian¹,Xiong Yuang¹,Madany Waleed¹,Shirane Atsushi¹,Okada Kenichi¹

Affiliation:

1. Tokyo Institute of Technology,,Tokyo,Japan

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10121189/10121178/10121180.pdf?arnumber=10121180

Reference4 articles.

1. A Fully Synthesizable Fractional-N MDLL With ZeroOrder Interpolation-Based DTC Nonlinearity Calibration and TwoStep Hybrid Phase Offset Calibration;liu;TCAS-I,2021

2. A 2.4-GHz 6.4-mW Fractional-N Inductorless RF Synthesizer

3. A 28-GHz Quadrature Fractional-N Frequency Synthesizer for 5G Transceivers With Less Than 100-fs Jitter Based on Cascaded PLL Architecture

4. A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur

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2. A 66.7fs-Integrated-Jitter Fractional-N Digital PLL Based on a Resistive-Inverse-Constant-Slope DTC;2024 IEEE Custom Integrated Circuits Conference (CICC);2024-04-21

3. A 59.3fs Jitter and -62.1dBc Fractional-Spur Digital PLL Based on a Multi-Edge Power-Gating Phase-Detector;2024 IEEE Custom Integrated Circuits Conference (CICC);2024-04-21

4. 10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fs_rms Integrated Jitter and −252.4dB FoM;2024 IEEE International Solid-State Circuits Conference (ISSCC);2024-02-18

5. A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier;IEEE Journal of Solid-State Circuits;2023-12