10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fs<sub>rms</sub> Integrated Jitter and −252.4dB FoM-Reference-Cited by-同舟云学术

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10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fs_rms Integrated Jitter and −252.4dB FoM

Published:2024-02-18 Issue: Volume: Page:188-190
ISSN:
Container-title:2024 IEEE International Solid-State Circuits Conference (ISSCC)
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Author:

Rossoni Michele¹,Dartizio Simone Mattia¹,Tesolin Francesco¹,Castoro Giacomo¹,Dell’Orto Riccardo¹,Samori Carlo¹,Lacaita Andrea Leonardo¹,Levantino Salvatore¹

Affiliation:

1. Politecnico di Milano,Milan,Italy

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10454133/10454267/10454388.pdf?arnumber=10454388

Reference10 articles.

1. 4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering

2. 32.1 A 365fsrms-Jitter and -63dBc-Fractional Spur 5.3GHz-Ring-DCO-Based Fractional-N DPLL Using a DTC Second/Third- Order Nonlinearity Cancelation and a Probability-Density-Shaping ΔΣM

3. Power‐jitter trade‐off analysis in digital‐to‐time converters

4. A 28-nm 75-fsrms Analog Fractional-$N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction

5. A 6.5-to-8GHz Cascaded Dual-Fractional-N Digital PLL Achieving -63.7dBc Fractional Spurs with 50MHz Reference

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