A 100 µW Decimator for a 16 bit 24 kHz bandwidth Audio ΔΣ Modulator
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/5512009/5536941/05537170.pdf?arnumber=5537170
Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A 13.5 mW Decimator for a 20 MHz bandwidth CTΔΣ Modulator using poly-phase decomposition techniques;2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS);2023-12-04
2. Design and implementation of a new high-accuracy interpolation encoder IC for magneto-resistive sensors;Microsystem Technologies;2020-07-13
3. Low Power Design Techniques for Single-Bit Audio Continuous-Time Delta Sigma ADCs Using FIR Feedback;IEEE Journal of Solid-State Circuits;2014-11
4. An error-feedback noise-shaping SAR ADC in 90 nm CMOS;Analog Integrated Circuits and Signal Processing;2014-10-28
5. A Third-Order Switched-Current Delta-Sigma Modulator with Analog Error Cancellation Logic and Digital Comb Filter;IEICE Transactions on Electronics;2013
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