An error-feedback noise-shaping SAR ADC in 90 nm CMOS-Reference-Cited by-同舟云学术

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An error-feedback noise-shaping SAR ADC in 90 nm CMOS

Published:2014-10-28 Issue:3 Volume:81 Page:805-814
ISSN:0925-1030
Container-title:Analog Integrated Circuits and Signal Processing
language:en
Short-container-title:Analog Integr Circ Sig Process

Author:

Shahghasemi Mohsen,Inanlou Reza,Yavari Mohammad

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Link

http://link.springer.com/content/pdf/10.1007/s10470-014-0434-6.pdf

Reference29 articles.

1. Verma, N., & Chandrakasan, A. P. (2007). An ultra low energy 12-bit rate-resolution scalable SAR ADC for wireless sensor nodes. IEEE Journal of Solid-State Circuits, 42(6), 1196–1205.

2. Cho, S.-H., Lee, C.-K., Kwon, J.-K., & Ryu, S–. K. (2011). A 550-μW 10-b 40-MS/s SAR ADC with multistep addition-only digital error correction. IEEE Journal of Solid-State Circuits, 46(8), 1881–1892.

3. Agnes, A., Bonizzoni, E., Malcovati, P., & Maloberti, F. (2010). An ultra-low power successive approximation A/D converter with time-domain comparator. Journal of Analog Integrated Circuits and Signal Processing, 64(2), 183–190.

4. Zhang, D., Bhide, A., & Alvandpour, A. (2012). A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13-μm CMOS for medical implant devices. IEEE Journal of Solid-State Circuits, 47(7), 1585–1593.

5. McCreary, J. L., & Gray, P. R. (1975). All-MOS charge redistribution analog-to-digital conversion techniques. I. IEEE Journal of Solid-State Circuits, 10(6), 371–379.

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3. Arithmetic Tracking Adaptive SAR ADC for Signals With Low-Activity Periods;IEEE Access;2020

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