Adaptive Clock Gating Technique for Low Power IP Core in SoC Design-Reference-Cited by-同舟云学术

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Adaptive Clock Gating Technique for Low Power IP Core in SoC Design

Published:2007-05 Issue: Volume: Page:
ISSN:
Container-title:2007 IEEE International Symposium on Circuits and Systems
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Author:

Chang Xiaotao,Zhang Mingming,Zhang Ge,Zhang Zhimin,Wang Jun

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/4252534/4252535/04253089.pdf?arnumber=4253089

Cited by 15 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. On-chip supply noise in multiprocessors: impact and clock gating inspired mitigation strategies;International Journal of Electronics;2022-12-28

2. Insert & Save: Energy Optimization in IP Core Integration for FPGA-based Real-time Systems;2021 IEEE 27th Real-Time and Embedded Technology and Applications Symposium (RTAS);2021-05

3. Forensic engineering for resolving ownership problem of reusable IP core generated during high level synthesis;Future Generation Computer Systems;2018-03

4. Exercising Symbolic Discrete Control for Designing Low-power Hardware Circuits: an Application to Clock-gating;IFAC-PapersOnLine;2018

5. Cache Power Optimization Based on Compare‐Based Adaptive Clock Gating and Its 65nm SoC Implementation;Chinese Journal of Electronics;2017-01

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