Author:
Yoshizawa Shingo,Orikasa Atsushi,Miyanaga Yoshikazu
Cited by
8 articles.
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1. Multiplexer & Memory Efficient Bit-Reversal Algorithms;2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS);2023-11-19
2. A Novel Digital Logic for Bit Reversal and Address Generations in FFT Computations;Wireless Personal Communications;2022-09-11
3. Multi-Channel FFT Architectures Designed via Folding and Interleaving;2022 IEEE International Symposium on Circuits and Systems (ISCAS);2022-05-28
4. A Survey on Pipelined FFT Hardware Architectures;Journal of Signal Processing Systems;2021-07-06
5. A high-speed MIMO FFT processor with full hardware utilization;International Journal of Circuit Theory and Applications;2018-06-04