A Survey on Pipelined FFT Hardware Architectures-Reference-Cited by-同舟云学术

A Survey on Pipelined FFT Hardware Architectures

Published:2021-07-06 Issue: Volume: Page:
ISSN:1939-8018
Container-title:Journal of Signal Processing Systems
language:en
Short-container-title:J Sign Process Syst

Author:

Garrido Mario^ORCID

Abstract

AbstractThe field of pipelined FFT hardware architectures has been studied during the last 50 years. This paper is a survey that includes the main advances in the field related to architectures for complex input data and power-of-two FFT sizes. Furthermore, the paper is intended to be educational, so that the reader can learn how the architectures work. Finally, the paper divides the architectures into serial and parallel. This classification puts together those architectures that are conceived for a similar purpose and, therefore, are comparable.

Funder

Ministerio de Ciencia, Innovación y Universidades

Publisher

Springer Science and Business Media LLC

Subject

Hardware and Architecture,Modeling and Simulation,Information Systems,Signal Processing,Theoretical Computer Science,Control and Systems Engineering

Link

https://link.springer.com/content/pdf/10.1007/s11265-021-01655-1.pdf

Reference90 articles.

1. Abdullah, S., Nam, H., McDermot, M., & Abraham, J. (2009). A high throughput FFT processor with no multipliers. In Proc. IEEE int. Conf. Comput. design (pp. 485–490).

2. Adiono, T., Irsyadi, M. S., & Hidayat, Y. S. (2009). Irawan, a.: 64-point fast efficient FFT architecture using radix-23 single path delay feedback. In Proc. Int. Conf. Electrical engineering informatics, (Vol. 02 pp. 654–658).

3. Ahmed, T. (2013). A low-power time-interleaved 128-point FFT for IEEE 802.15.3c standard. In Proc. Int. Conf. Informatics electron. vision (pp. pp. 1–5).

4. Ahmed, T., Garrido, M., & Gustafsson, O. (2011). A 512-point 8-parallel pipelined feedforward FFT for WPAN. In Proc. Asilomar conf. Signals syst. Comput. (pp. 981–984).

5. Ayinala, M., Brown, M., & Parhi, K. K. (2012). Pipelined parallel FFT, architectures via folding transformation. IEEE Trans. VLSI Syst., 20(6), 1068–1081.

Cited by 42 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Coarse-grained reconfigurable architectures for radio baseband processing: A survey;Journal of Systems Architecture;2024-09

2. FFT on a Heterogeneous System with a General-Purpose Map-Scan Accelerator;Romanian Journal of Information Science and Technology;2024-06-27

3. FPGA real-time implementation of welch transform for diagnosis of broken rotor bars in induction motors;Electrical Engineering;2024-06-20

4. Soft GPGPU versus IP cores: Quantifying and Reducing the Performance Gap;14th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART'24));2024-06-19

5. A Low-footprint FFT Accelerator for a RISC-V-based Multi-core DSP in FMCW Radars;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19