Abstract
AbstractThe field of pipelined FFT hardware architectures has been studied during the last 50 years. This paper is a survey that includes the main advances in the field related to architectures for complex input data and power-of-two FFT sizes. Furthermore, the paper is intended to be educational, so that the reader can learn how the architectures work. Finally, the paper divides the architectures into serial and parallel. This classification puts together those architectures that are conceived for a similar purpose and, therefore, are comparable.
Funder
Ministerio de Ciencia, Innovación y Universidades
Publisher
Springer Science and Business Media LLC
Subject
Hardware and Architecture,Modeling and Simulation,Information Systems,Signal Processing,Theoretical Computer Science,Control and Systems Engineering
Cited by
28 articles.
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