Multi-Channel FFT Architectures Designed via Folding and Interleaving
Author:
Affiliation:
1. University of Minnesota,Dept. Electrical and Computer Engineering,Minneapolis,MN,USA
Funder
National Science Foundation
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9937201/9937203/09937347.pdf?arnumber=9937347
Reference21 articles.
1. Effect of Finite Word-Length on SQNR, Area and Power for Real-Valued Serial FFT
2. A Serial Commutator Fast Fourier Transform Architecture for Real-Valued Signals
3. FFT Architectures for Real-Valued Signals Based on Radix-$2^{3}$ and Radix-$2^{4}$ Algorithms
4. A Novel Memory-Based FFT Architecture for Real-Valued Signals Based on a Radix-2 Decimation-In-Frequency Algorithm
5. A High-Speed Two-Parallel Radix-24 FFT/IFFT Processor for MB-OFDM UWB Systems
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1. Area-Efficient Matrix-Vector Polynomial Multiplication Architecture for ML-KEM Using Interleaving and Folding Transformation;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
2. A Low-Latency Fft-Ifft Cascade Architecture;ICASSP 2024 - 2024 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP);2024-04-14
3. InterGrad: Energy-Efficient Training of Convolutional Neural Networks via Interleaved Gradient Scheduling;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-05
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