An In-DRAM Neural Network Processing Engine

Author:

Sudarshan Chirag1,Lappas Jan1,Ghaffar Muhammad Mohsin1,Rybalkin Vladimir1,Weis Christian1,Jung Matthias2,Wehn Norbert1

Affiliation:

1. Technische Universität Kaiserslautern, Germany

2. Fraunhofer Institute for Experimental Software Engineering (IESE), Germany

Publisher

IEEE

Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. HiFi-DRAM: Enabling High-fidelity DRAM Research by Uncovering Sense Amplifiers with IC Imaging;2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA);2024-06-29

2. FeFET versus DRAM based PIM Architectures: A Comparative Study;2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC);2022-10-03

3. A Weighted Current Summation Based Mixed Signal DRAM-PIM Architecture for Deep Neural Network Inference;IEEE Journal on Emerging and Selected Topics in Circuits and Systems;2022-06

4. Optimization of DRAM based PIM Architecture for Energy-Efficient Deep Neural Network Training;2022 IEEE International Symposium on Circuits and Systems (ISCAS);2022-05-28

5. Efficient Machine Learning execution with Near-Data Processing;Microprocessors and Microsystems;2022-04

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