FeFET versus DRAM based PIM Architectures: A Comparative Study

Author:

Sudarshan Chirag1,Soliman Taha2,Kampfe Thomas3,Weis Christian1,Wehn Norbert1

Affiliation:

1. University of Kaiserslauten,Kaiserslauten,Germany

2. Robert Bosch GmbH,Renningen,Germany

3. Center Nanoelectronic Technologies (CNT),Fraunhofer IPMS,Dresden,Germany

Publisher

IEEE

Reference46 articles.

1. Ten Lessons From Three Generations Shaped Google’s TPUv4i : Industrial Product;jouppi;2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA),2021

2. HBM: Memory solution for bandwidth-hungry processors;kim;2014 IEEE Hot Chips 26 Symposium (HCS) IEEE,2014

3. A 1ynm 1.25V 8Gb, 16Gb/s/pin GDDR6-based Accelerator-in-Memory supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep-Learning Applications

4. Newton: A DRAM-maker’s Accelerator-in-Memory (AiM) Architecture for Machine Learning

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