A 1.85fW/bit ultra low leakage 10T SRAM with speed compensation scheme-Reference-Cited by-同舟云学术

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A 1.85fW/bit ultra low leakage 10T SRAM with speed compensation scheme

Published:2011-05 Issue: Volume: Page:
ISSN:
Container-title:2011 IEEE International Symposium of Circuits and Systems (ISCAS)
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Author:

Kim Daeyeon,Chen Gregory,Fojtik Matthew,Seok Mingoo,Blaauw David,Sylvester Dennis

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/5910713/5937406/05937503.pdf?arnumber=5937503

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 1.0 fJ energy/bit single‐ended 1 kb 6T SRAM implemented using 40 nm CMOS process;IET Circuits, Devices & Systems;2023-01-10

2. A 22nm CMOS 0.2V 13.3nW 16T SRAM Using Dynamic Leakage Suppression and Half-Selected Free Technique;2021 IEEE Asia Pacific Conference on Circuit and Systems (APCCAS);2021-11-22

3. A Single-Ended 28-nm CMOS 6T SRAM Design with Read-assist Path and PDP Reduction Circuitry;Journal of Circuits, Systems and Computers;2019-08-13

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