A Single-Ended 28-nm CMOS 6T SRAM Design with Read-assist Path and PDP Reduction Circuitry

Author:

Wang Chua-Chin1ORCID,Hou Zong-You1,Wang Deng-Shian1,Hsieh Chia-Lung1

Affiliation:

1. Department of Electrical Engineering, National Sun Yat-Sen University, No. 70 Lian-Hai Road, Kaohsiung 80424, Taiwan, R. O. P. R. China

Abstract

A single-ended six-transistor (6T) SRAM cell composed of a five-transistor (5T) cell and a read-assist low-[Formula: see text] PMOS as foot switch to prevent leakage damaging the data state is proposed in this work. Besides, a power–delay product (PDP) reduction circuitry design for nanoscale SRAMs is also proposed. The proposed PDP reduction circuitry design is composed of an adaptive voltage detection (AVD) circuit generating a boost-enable signal if the process variation is over a predefined range and a half-period word-line boosting (HWB) circuit responding to the enable signal. The proposed SRAM is implemented using TSMC 28-nm CMOS logic technology. PDP reduction is verified to be 41.73% according to the measurement results. The energy per access is 0.0206 pJ given the 800-mV power supply and 40-MHz system clock rate.

Funder

the Ministry of Science and Technology under the Grants

Publisher

World Scientific Pub Co Pte Lt

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Electrical and Electronic Engineering,Hardware and Architecture

Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Low power and noise‐immune 9 T compute SRAM cell design based on differential power generator and Schmitt‐trigger logics with14 nm FinFET technology;International Journal of Circuit Theory and Applications;2024-06-27

2. Analysis of Cache Memory Circuit for Compute In Memory Applications;2023 4th International Conference on Signal Processing and Communication (ICSPC);2023-03-23

3. A 1.0 fJ energy/bit single‐ended 1 kb 6T SRAM implemented using 40 nm CMOS process;IET Circuits, Devices & Systems;2023-01-10

4. A Single-Ended Low Power 16-nm FinFET 6T SRAM Design With PDP Reduction Circuit;IEEE Transactions on Circuits and Systems II: Express Briefs;2021-12

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