A 90 nm leakage control transistor based clock gating for low power flip flop applications-Reference-Cited by-同舟云学术

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A 90 nm leakage control transistor based clock gating for low power flip flop applications

Published:2016-10 Issue: Volume: Page:
ISSN:
Container-title:2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS)
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Author:

Bhattacharjee Pritam,Majumder Alak,Das Tushar Dhabal

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7862453/7869936/07870034.pdf?arnumber=7870034

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Trade-offs and Optimization: Low Power Approaches for Area, Power Consumption, and Performance in Microprocessor Design;2023 IEEE Regional Symposium on Micro and Nanoelectronics (RSM);2023-08-28

2. Low Area-High Speed Architecture of Efficient FIR Filter Using Look Ahead Clock Gating Technique;Advances in Cognitive Science and Communications;2023

3. On-chip supply noise in multiprocessors: impact and clock gating inspired mitigation strategies;International Journal of Electronics;2022-12-28

4. Low-Power High-Speed Eight-Bit Universal Shift Register Design Using Clock Gating Technique;Advances in Computer and Electrical Engineering;2022-12-16

5. A Variation-Aware Robust Gated Flip-Flop for Power-Constrained FSM Application;Journal of Circuits, Systems and Computers;2019-06-27

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