A Concurrent Testing Scheme for Muller Circuits Using Reduced Ordered Binary Decision Diagram
Author:
Affiliation:
1. IIIT Bhagalpur,Department of Computer Science & Engineering,Bihar,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9864330/9864331/09864357.pdf?arnumber=9864357
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1. Ways to set up a concurrent error detection system for logical circuits without memory
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4. Fifty Years of Moore's Law
5. Online test vector insertion: A concurrent built-in self-testing (CBIST) approach for asynchronous logic
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