An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA-Reference-Cited by-同舟云学术

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An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA

Published:2008 Issue: Volume: Page:
ISSN:
Container-title:2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools
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Author:

Fier Petr,Kubalík Pavel,Kubátová Hana

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/4669199/4669200/04669224.pdf?arnumber=4669224

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Concurrent Testing Scheme for Muller Circuits Using Reduced Ordered Binary Decision Diagram;2022 IEEE Region 10 Symposium (TENSYMP);2022-07-01

2. A Binary Decision Diagram Approach to On-line Testing of Asynchronous Circuits with Dynamic and Static C-elements;Journal of Electronic Testing;2019-10

3. A Binary Decision Diagram Approach to On-line Testing of Asynchronous Circuits;2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID);2019-01

4. Error masking method based on the short-duration offline test;Microprocessors and Microsystems;2017-07

5. A Fast SOP Minimizer for Logic Funcions Described by Many Product Terms;2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools;2009-08

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