Ways to set up a concurrent error detection system for logical circuits without memory-Reference-Cited by-同舟云学术

Ways to set up a concurrent error detection system for logical circuits without memory

Published:2016-05 Issue:5 Volume:87 Page:286-288
ISSN:1068-3712
Container-title:Russian Electrical Engineering
language:en
Short-container-title:Russ. Electr. Engin.

Author:

Efanov D. V.,Groshev G. M.,Malikov O. B.

Publisher

Allerton Press

Subject

Electrical and Electronic Engineering

Link

http://link.springer.com/content/pdf/10.3103/S1068371216050060.pdf

Reference12 articles.

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2. Ubar, R., Raik, J., and Vierhaus, H.-T., Design and test technology for dependable systems-on-chip (premier reference source), in Information Science Reference, Hershey–New York: IGI Global, 2011.

3. Nicolaidis, M. and Zorian, Y., On-line testing for VLSI–a compendium of approaches, J. Electron. Testing: Theory Appl., 1998, no. 12.

4. Mitra, S. and McClaskey, E.J., Which concurrent error detection scheme to choose?, Proc. Int. Test Conf., Atlantic City, NJ, Oct. 3–5, 2000.

5. Fujiwara, E., Code Design for Dependable Systems: Theory and Practical Applications, New Jersey: John Wiley & Sons, 2006.

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