3D stacked chip technology using bottom-up electroplated TSVs-Reference-Cited by-同舟云学术

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3D stacked chip technology using bottom-up electroplated TSVs

Published:2009-05 Issue: Volume: Page:
ISSN:
Container-title:2009 59th Electronic Components and Technology Conference
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Author:

Chang H. H.,Shih Y. C.,Hsiao Z. C.,Chiang C. W.,Chen Y. H.,Chiang K. N.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/5066986/5073977/05074161.pdf?arnumber=5074161

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Microsystems using three-dimensional integration and TSV technologies: Fundamentals and applications;Microelectronic Engineering;2019-04

2. Development of seed layer deposition and fast copper electroplating into deep microvias for three‐dimensional integration;Micro & Nano Letters;2013-04

3. Wafer-level three-dimensional integrated circuits (3D IC): Schemes and key technologies;Microelectronic Engineering;2011-11

4. Novel sequential electro-chemical and thermo-mechanical simulation methodology for annular through-silicon-via (TSV) design;2010 Proceedings 60th Electronic Components and Technology Conference (ECTC);2010

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