Opportunities in 3-D stacked CMOS transistors-Reference-Cited by-同舟云学术

Opportunities in 3-D stacked CMOS transistors

Published:2021-12-11 Issue: Volume: Page:
ISSN:
Container-title:2021 IEEE International Electron Devices Meeting (IEDM)
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Author:

Radosavljevic M.¹,Huang C.-Y.¹,Rachmady W.¹,Seung S.H.¹,Thomas N. K.¹,Dewey G.¹,Agrawal A.¹,Owens K.¹,Kuo C. C.¹,Jezewski C. J.¹,Nahm R.¹,Briggs N.¹,Tronic T. A.¹,Michaelos T.¹,Kabir N. A.¹,Holybee B.¹,Jun K.¹,Morrow P.¹,Phan A.¹,Shivaraman S.¹,Then H. W.¹,Kapinus V.²,Harper M. K.²,Nguyen P. D.²,Cheong K. L.²,Ghose S.²,Ganguly K.²,Bomberger C.²,Tan J. M.²,El Qader M. Abd²,Oni A. A.³,Fischer P.¹,Bristol R.¹,Metz M.¹,Clendenning S. B.¹,Turkot B.¹,Schenker R.¹,Kobrinsky M. J.¹,Kavalieros J.¹

Affiliation:

1. Components Research

2. Technology Development

3. Quality and Reliability, Intel Corporation,Hillsboro,OR,97124

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9720433/9720494/09720633.pdf?arnumber=9720633

Reference13 articles.

1. A Stacked CMOS Technology on SOI Substrate

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