Towards Improved Nanosheet-Based Complementary Field Effect Transistor (CFET) Performance Down to 42nm Contacted Gate Pitch
Author:
Affiliation:
1. imec, Kapeldreef 75,Leuven,Belgium,3001
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10511270/10511310/10512269.pdf?arnumber=10512269
Reference12 articles.
1. A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors
2. A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications
3. PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch
4. First Monolithic Integration of 3D Complementary FET (CFET) on 300mm Wafers
5. 3-D Self-aligned Stacked NMOS-on-PMOS Nanoribbon Transistors for Continued Moore’s Law Scaling
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