Monolithic 3-D Self-Aligned Heterogeneous Nanosheet Channel Complementary FETs With Matched VT by Band Alignments of Individual Channels

Author:

Hsieh Wan-Hsuan1ORCID,Tu Chien-Te1ORCID,Chen Yu-Rui1ORCID,Huang Bo-Wei1ORCID,Chen Wei-Jen1,Liu Yi-Chun1ORCID,Cheng Chun-Yi1ORCID,Chou Hung-Chun2ORCID,Liu C. W.3ORCID

Affiliation:

1. Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan

2. Graduate School of Advanced Technology, National Taiwan University, Taipei, Taiwan

3. Department of Electrical Engineering, the Graduate Institute of Electronics Engineering, the Graduate Institute of Photonics and Optoelectronics, and the Graduate School of Advanced Technology, National Taiwan University, Taipei, Taiwan

Funder

T-Star center project “Future Semiconductor Technology Research Center”

National Science and Technology Council, Taiwan

Ministry of Education (MOE), Taiwan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Reference20 articles.

1. A 14 nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 μm2 SRAM cell size;Natarajan

2. High performance 14 nm SOI FinFET CMOS technology with 0.0174 μm2 embedded DRAM and 15 levels of cu metallization;Lin

3. An enhanced 16 nm CMOS technology featuring 2nd generation FinFET transistors and advanced Cu/low-K interconnect for low power and high performance applications;Wu

4. High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling

5. Si nanowire CMOS fabricated with minimal deviation from RMG FinFET technology showing record performance

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