Comparison of Electrical Performance of Co-Integrated Forksheets and Nanosheets Transistors for the 2nm Technological Node and Beyond-Reference-Cited by-同舟云学术

Comparison of Electrical Performance of Co-Integrated Forksheets and Nanosheets Transistors for the 2nm Technological Node and Beyond

Published:2021-12-11 Issue: Volume: Page:
ISSN:
Container-title:2021 IEEE International Electron Devices Meeting (IEDM)
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Author:

Ritzenthaler R.¹,Mertens H.¹,Eneman G.¹,Simoen E.¹,Bury E.¹,Eyben P.¹,Bufler F. M.¹,Oniki Y.¹,Briggs B.¹,Chan B.T.¹,Hikavyy A.¹,Mannaert G.¹,Parvais B.¹,Chasin A.¹,Mitard J.¹,Litta E. Dentoni¹,Samavedam S.¹,Horiguchi N.¹

Affiliation:

1. IMEC,Leuven,Belgium

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9720433/9720494/09720524.pdf?arnumber=9720524

Reference13 articles.

1. Assessment of the stochastic nature of dielectric breakdown in advanced CMOS technologies utilizing voltage ramp stress methodology;kerber;IEDM Tech Dig,2019

2. A Low-Power HKMG CMOS Platform Compatible With Dram Node 2× and Beyond

3. Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gates

4. Vertically Stacked Gate-All-Around Si Nanowire CMOS Transistors with Reduced Vertical Nanowires Separation, New Work Function Metal Gate Solutions, and DC/AC Performance Optimization

5. Novel forksheet device architecture as ultimate logic scaling device towards 2nm

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