Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gates-Reference-Cited by-同舟云学术

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Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gates

Published:2016-12 Issue: Volume: Page:
ISSN:
Container-title:2016 IEEE International Electron Devices Meeting (IEDM)
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Author:

Mertens H.,Ritzenthaler R.,Chasin A.,Schram T.,Kunnen E.,Hikavyy A.,Ragnarsson L.-A.,Dekkers H.,Hopf T.,Wostyn K.,Devriendt K.,Chew S. A.,Kim M. S.,Kikuchi Y.,Rosseel E.,Mannaert G.,Kubicek S.,Demuynck S.,Dangol A.,Bosman N.,Geypen J.,Carolan P.,Bender H.,Barla K.,Horiguchi N.,Mocuta D.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7824662/7838021/07838456.pdf?arnumber=7838456

Cited by 48 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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4. Design Technology Co-Optimization for Gate-All-Around Nanosheet Transistors Considering Source/Drain Confinement and Post- Gate Single Diffusion Break;IEEE Transactions on Electron Devices;2024-07

5. Comprehensive Analysis of Sheet Thickness Scaling on the Performance of Nanosheet nFETs;IEEE Transactions on Electron Devices;2024-05

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