Design of low power high speed full adder cell with XOR/XNOR logic gates

Author:

Alluri Sudhakar,Dasharatha M.,Naik B. Rajendra,Reddy N. S. S.

Publisher

IEEE

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. An Efficient Full Adder by Investigating XOR and XNOR Logics with PMOS and NMOS;2023 3rd International Conference on Pervasive Computing and Social Networking (ICPCSN);2023-06

2. Exploring XOR-based Full Adders and decoupling cells to variability mitigation at FinFET technology;Integration;2022-11

3. Mirror Full Adder SET Susceptibility on 7nm FinFET Technology;2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS);2020-11-23

4. Mitigation Effects of Decoupling Cells on Full Adders Process Variability;2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS);2020-08

5. Low Power Adder Circuit Based on Coupling Technique;Advances in Intelligent Systems and Computing;2018

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