An Efficient Full Adder by Investigating XOR and XNOR Logics with PMOS and NMOS
Author:
Affiliation:
1. K. Ramakrishanan College of Engineering,Department of Electronics and Communication Engineering,Tiruchirappalli,India,621112
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10265860/10265772/10266171.pdf?arnumber=10266171
Reference15 articles.
1. Optimized low power full adder design
2. A new design of the CMOS full adder
3. Design and Analysis of Low-Power 10-Transistor Full Adders Using Novel XOR-XNOR Gates;bui;IEEE Transactions on Circuits and Systems Analog and Digital Signal Processing,2002
4. Design of low power high speed full adder cell with XOR/XNOR logic gates
5. Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit;gowtham;Turkish Journal of Computer and Mathematics Education,2021
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