Author:
Wairya Subodh,Singh Garima,Vishant ,Nagaria R. K.,Tiwari S.
Cited by
8 articles.
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1. Performance Analysis of Low Power Hybrid Full Adder Using Pass Transistor Logic;2024 IEEE International Conference on Interdisciplinary Approaches in Technology and Management for Social Innovation (IATMSI);2024-03-14
2. A Comparative Analysis and Ideas to Reduce Various Leakage Power in Modern VLSI;Nanoscale Field Effect Transistors: Emerging Applications;2023-12-19
3. Performance Evaluation of Efficient Low Power 1-bit Hybrid Full Adder;ADCAIJ: Advances in Distributed Computing and Artificial Intelligence Journal;2023-06-05
4. Performance Enhancement of Conventional Design of 4-Bit Carry Look-Ahead Adder;2023 3rd International Conference on Robotics, Electrical and Signal Processing Techniques (ICREST);2023-01-07
5. A Low Power High Speed 15T FinFET-GDI Based Hybrid Full Adder Using 18 nm Technology;Lecture Notes in Electrical Engineering;2022