A Comparative Analysis and Ideas to Reduce Various Leakage Power in Modern VLSI-Reference-Cited by-同舟云学术

A Comparative Analysis and Ideas to Reduce Various Leakage Power in Modern VLSI

Published:2023-12-19 Issue: Volume: Page:177-191
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Container-title:Nanoscale Field Effect Transistors: Emerging Applications
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Author:

Sravana J.¹,Karthik A.²,Dinesh T.³

Affiliation:

1. Geethanjali College of Engineering, Hyderabad, India

2. Institute of Aeronautical Engineering, Hyderabad, India

3. Anurag University, Hyderabad, India

Abstract

In today's high-performance chips, comparative analysis and ideas for reducing power consumption have become the dominant factor in overall power consumption. This should reduce the power consumption of high-density chips, which is so great that many new techniques have been developed in the proposal to design low-power circuits and systems. Ultra-thin gate oxides, very low threshold voltages, and short channels are hallmarks of nanoscale chips. Therefore, the most difficult problem that arises in VLSI circuits and systems is power dissipation. This paper provides an overview of sources of leakage currents in sub-micrometer CMOS gates and techniques, limitations, analysis and ideas to reduce leakage currents [1]; an overview of current circuit-level leakage currents [2] for various techniques; also discusses an example of a 1-bit adiabatic ECRL adder which compares the power and delay. This is one way of leakage minimization technique which is caused by switching action. This simulation work is done in cadence tool using FINFET technology which is a very fast-growing technology as compared to CMOS technology [3].

Publisher

BENTHAM SCIENCE PUBLISHERS

Reference12 articles.

1. Akshitha N.; Power reduction of half adder and half subtractor using different partial adiabatic logic styles. International Conference on Intelligent Sustainable Systems (ICISS 2019), in IEEE Xplore, Vol. 9, no. 1, 2019.

2. Kendri S.S.; Khanai R.; Mavinkattimath S.; Partial Adiabatic Logic. Int J Comput Appl 2018 ,8(4),978-983

3. Sravana J.; Indrani K.S.; Sankeerth Mahurkar M.; Optimized VLSI Design of Squaring Multiplier Using Yavadunam Sutra Through Deficiency Bits Reduction. Advances in Signal Processing and Communication Engineering Select Proceedings of ICASPACE 2021 in Springer Nature Singapore, 2021.

4. Zobiri O.; Atia A.; Arıcı M.; Analysis of heat conduction in a nanoscale metal oxide semiconductor field effect transistor using lattice Boltzmann method. Energy Sources A Recovery Util Environ Effects 2020

5. Cutitaru L.A.; Arithmetic circuits using new singlephase partially adiabatic logic family. IEEE Transactions on VLSI Systems 2013 ,8(4),978-983