A Low Power High Speed 15T FinFET-GDI Based Hybrid Full Adder Using 18 nm Technology
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Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-19-2631-0_39
Reference16 articles.
1. Hasan, M., Hossein, M.J., Saha, U.K., Tarif, M.S.: Overview and comparative performance analysis of various full adder cells in 90 nm technology. In: 4th International Conference on Computing Communication and Automation (ICCCA), pp. 1–6 (2018). https://doi.org/10.1109/CCAA.2018.8777684
2. Mewada, M., Zaveri, M.: A low-power high-speed hybrid full adder. In: 2016 20th International Symposium on VLSI Design and Test (VDAT), pp. 1–2 (2016). https://doi.org/10.1109/ISVDAT.2016.8064900
3. Goel, S., Kumar, A., Bayoumi, M.A.: Design of robust, energy-efficient full adders for deep-submicrometer design using hybrid-CMOS logic style. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 14, 1309–1321 (2006). https://doi.org/10.1109/TVLSI.2006.887807
4. Kadu, C.P., Sharma, M.: Area-efficient high-speed hybrid 1-bit full adder circuit using modified XNOR gate. In: 2017 International Conference on Information, Communication, Instrumentation and Control (ICICIC), pp. 1–5 (2017). https://doi.org/10.1109/ICOMICON.2017.8279064
5. Theja, M.N., Balakumaran, T.: Energy efficient low power high speed full adder design using hybrid logic. In: 2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT), pp. 1–8 (2016). https://doi.org/10.1109/ICCPCT.2016.7530209
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