Device Analysis of Vertically Stacked GAA Nanosheet FET at Advanced Technology Node-Reference-Cited by-同舟云学术

Device Analysis of Vertically Stacked GAA Nanosheet FET at Advanced Technology Node

Published:2023-05-18 Issue: Volume: Page:
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Container-title:2023 3rd International Conference on Advances in Computing, Communication, Embedded and Secure Systems (ACCESS)
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Author:

Kumar Aruru Sai¹,Deekshana M.¹,Sreenivasulu V. Bharath²,Kumari N. Aruna³,Shanthi G.¹

Affiliation:

1. VNR VJIET,Department of ECE,Hyderabad,India,500090

2. IIT Patna,Department of Electrical Engineering,Patna,India,801106

3. VIT University Vellore,Department of SENSE,Vellore,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10199116/10199143/10199820.pdf?arnumber=10199820

Reference37 articles.

1. Design and Deep Insights into Sub-10 nm Spacer Engineered Junctionless FinFET for Nanoscale Applications;sreenivasulu;ECS J Solid State Sci Technol,2021

2. Implementation of High speed and Low power 6T SRAM cell using FinFET at 22nm technology

3. Characterization and optimization of junctionless gate-all-around vertically stacked nanowire FETs for sub-5 nm technology nodes

4. Mongoose OS Prototyped ESP8266 Based Weather Forecaster

5. Device and circuit-level performance comparison of GAA nanosheet FET with varied geometrical parameters

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