Characterization and optimization of junctionless gate-all-around vertically stacked nanowire FETs for sub-5 nm technology nodes-Reference-Cited by-同舟云学术

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Characterization and optimization of junctionless gate-all-around vertically stacked nanowire FETs for sub-5 nm technology nodes

Published:2021-10 Issue: Volume:116 Page:105214
ISSN:0026-2692
Container-title:Microelectronics Journal
language:en
Short-container-title:Microelectronics Journal

Author:

Sreenivasulu V. Bharath^ORCID,Narendar Vadthiya

Publisher

Elsevier BV

Subject

General Engineering

Reference42 articles.

1. Considerations for ultimate CMOS scaling;Kuhn;IEEE Trans. Electron Devices,2012

2. A novel PNPN-like Z-shaped tunnel field-effect transistor with improved ambipolar behavior and RF performance;Imenabadi;IEEE Trans. Electron Devices,2017

3. Ground plane fin-shaped field effect transistor (GP-FinFET): A FinFET for low leakage power circuits;Saremi;Microelectron. Eng.,2012

4. A resonant tunneling nanowire field effect transistor with physical contractions: A negative differential resistance device for low power very large scale integration applications;Abadi;J. Electron. Mater.,2018

5. Performance improvement of spacer engineered n-type SOI FinFET at 3 nm gate length;Sreenivasulu;AEU-Int. J. Electron. Commun.,2021

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1. Novel SOI-MESFET for High-Frequency Operations: Improving Electric Field Distribution;Brazilian Journal of Physics;2024-08-13

2. Design insights into a junctionless nanosheet FET (JL-NSFET) for switching and Analog/RF applications: Device to circuit level assessment;Microelectronics Journal;2024-07

3. Design of high-K dielectric HSS-DMG Junctionless FinFET using hetero GOS for nanoscale application;Engineering Research Express;2024-06-01

4. Fabrication of the low-k films with tunable k value as spacers in advanced CMOS technology;Journal of Vacuum Science & Technology A;2024-02-29

5. Benchmarking of Multi-Bridge-Channel FETs Toward Analog and Mixed-Mode Circuit Applications;IEEE Access;2024

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