NVSystolic: Heterogeneous Simulation Framework for Emerging Memories with Systolic Array-Reference-Cited by-同舟云学术

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NVSystolic: Heterogeneous Simulation Framework for Emerging Memories with Systolic Array

Published:2023-07-03 Issue: Volume: Page:
ISSN:
Container-title:2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)
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Author:

Chithambara Moorthii J¹,Khanv Sufyan¹,Suri Manan¹

Affiliation:

1. Indian Institute of Technology Delhi,New Delhi,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10192100/10192102/10192216.pdf?arnumber=10192216

Reference15 articles.

1. Ternary cache: Three-valued MLC STT-RAM caches

2. Technology comparison for large last-level caches (L³Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM

3. An 8 Mb Multi-Layered Cross-Point ReRAM Macro With 443 MB/s Write Throughput

4. State Asymmetry Driven State Remapping in Phase Change Memory

5. CACTI 7

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