Technology comparison for large last-level caches (L<sup>3</sup>Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM-Reference-Cited by-同舟云学术

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Technology comparison for large last-level caches (L³Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM

Published:2013-02 Issue: Volume: Page:
ISSN:
Container-title:2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)
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Author:

Mu-Tien Chang ,Rosenfeld P.,Shih-Lien Lu ,Jacob B.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/6518038/6522298/06522314.pdf?arnumber=6522314

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