Author:
Sen Alper,Aksanli Baris,Bozkurt Murat,Mert Melih
Cited by
11 articles.
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1. CPGPUSim: A Multi-dimensional Parallel Acceleration Framework for RTL Simulation;2024 2nd International Symposium of Electronics Design Automation (ISEDA);2024-05-10
2. General-Purpose Gate-Level Simulation with Partition-Agnostic Parallelism;2023 60th ACM/IEEE Design Automation Conference (DAC);2023-07-09
3. Neural Network Compiler for Parallel High-Throughput Simulation of Digital Circuits;2023 IEEE International Parallel and Distributed Processing Symposium (IPDPS);2023-05
4. GATSPI;Proceedings of the 59th ACM/IEEE Design Automation Conference;2022-07-10
5. Accelerate Logic Re-simulation on GPU via Gate/Event Parallelism and State Compression;2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD);2021-11-01