Accelerate Logic Re-simulation on GPU via Gate/Event Parallelism and State Compression-Reference-Cited by-同舟云学术

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Accelerate Logic Re-simulation on GPU via Gate/Event Parallelism and State Compression

Published:2021-11-01 Issue: Volume: Page:
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Container-title:2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)
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Author:

Zeng Cheng,Yang Fan,Zeng Xuan

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9643423/9643432/09643571.pdf?arnumber=9643571

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. CPGPUSim: A Multi-dimensional Parallel Acceleration Framework for RTL Simulation;2024 2nd International Symposium of Electronics Design Automation (ISEDA);2024-05-10

2. Fast and Scalable Gate-Level Simulation in Massively Parallel Systems;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28

3. General-Purpose Gate-Level Simulation with Partition-Agnostic Parallelism;2023 60th ACM/IEEE Design Automation Conference (DAC);2023-07-09

4. GATSPI;Proceedings of the 59th ACM/IEEE Design Automation Conference;2022-07-10

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