Read-disturb Detection Methodology for RRAM-based Computation-in-Memory Architecture
Author:
Affiliation:
1. Delft University of Technology,Computer Engineering Lab,Delft,The Netherlands
2. IBM Research Division,Yorktown Heights,NY,USA
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10168547/10168548/10168638.pdf?arnumber=10168638
Reference21 articles.
1. A 40-nm MLC-RRAM Compute-in-Memory Macro With Sparsity Control, On-Chip Write-Verify, and Temperature-Independent ADC References
2. VSDCA: A Voltage Sensing Differential Column Architecture Based on 1T2R RRAM Array for Computing-in-Memory Accelerators
3. A closed-loop design to enhance weight stability of memristor based neural network chips
4. Investigation of Read Disturb and Bipolar Read Scheme on Multilevel RRAM-Based Deep Learning Inference Engine
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1. Dynamic Detection and Mitigation of Read-disturb for Accurate Memristor-based Neural Networks;2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS);2024-04-22
2. Reliable and Energy-Efficient Diabetic Retinopathy Screening Using Memristor-Based Neural Networks;IEEE Access;2024
3. Energy-efficient Computation-In-Memory Architecture using Emerging Technologies;2023 International Conference on Microelectronics (ICM);2023-12-17
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