VSDCA: A Voltage Sensing Differential Column Architecture Based on 1T2R RRAM Array for Computing-in-Memory Accelerators-Reference-Cited by-同舟云学术

VSDCA: A Voltage Sensing Differential Column Architecture Based on 1T2R RRAM Array for Computing-in-Memory Accelerators

Published:2022-10 Issue:10 Volume:69 Page:4028-4041
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Jing Zhaokun¹^ORCID,Yan Bonan²^ORCID,Yang Yuchao³^ORCID,Huang Ru³

Affiliation:

1. Key Laboratory of Microelectronic Devices and Circuits (MOE), School of Integrated Circuits, Peking University, Beijing, China

2. Institute for Artificial Intelligence and the Key Laboratory of Microelectronic Devices and Circuits (MOE), School of Integrated Circuits, Peking University, Beijing, China

3. Key Laboratory of Microelectronic Devices and Circuits (MOE), School of Integrated Circuits, and the Center for Brain Inspired Chips, Institute for Artificial Intelligence, Peking University, Beijing, China,

Funder

National Key Research and Development Program of China

National Natural Science Foundation of China

Peking University (PKU)-Baidu Fund

111 Project

Fok Ying Tong Education Foundation

Tencent Foundation through the Xplorer Prize

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture

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