Clock gated low power sequential circuit design
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx7/6550118/6558050/06558136.pdf?arnumber=6558136
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Analysis of Clock Gating Techniques for Low Power;Lecture Notes in Electrical Engineering;2024
2. A Partitioning Tool for Designing Low-Power Partitioned Finite-State Machines;2022 IEEE ANDESCON;2022-11-16
3. Low-Power FSM Synthesis Based on Automated Power and Clock Gating Technique;Journal of Circuits, Systems and Computers;2019-05
4. An Efficient Timing and Clock Tree Aware Placement Flow with Multibit Flip-Flops for Power Reduction;Communications in Computer and Information Science;2017
5. An Autonomous Power and Clock Gating Technique in SRAM-Based FPGA;Lecture Notes in Electrical Engineering;2017
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