Author:
Gulati Jasmine Kaur,Prakash Bhanu,Darak Sumit
Reference13 articles.
1. Lorincz, B.H., Cao, Y., Li, X., Mai, K., Pileggi, L.T., Rutenbar, R.A., Shepard, K.L.: Digital circuit design challenges and opportunities in the era of nanoscale CMOS. Proc. IEEE 96(2), 343–365 (2008)
2. Roy, S., Mattheakis, P.M., Masse-Navette, L., Pan, D.Z.: Evolving challenges and techniques for nanometer SoC clock network synthesis. In: 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), pp. 1–4, October 2014
3. Teng, S.K., Soin, N.: Low power clock gates optimization for clock tree distribution. In: 11th International Symposium on Quality Electronic Design (ISQED), pp. 488–492, March 2010
4. Dev, M.P., Baghel, D., Pandey, B., Pattanaik, M., Shukla, A.: Clock gated low power sequential circuit design. In: IEEE Conference on Information Communication Technologies (ICT), pp. 440–444, April 2013
5. Chen, S.Y., Lin, R.B., Tung, H.H., Lin, K.W.: Power gating design for standard-cell-like structured ASICs. In: Design, Automation Test in Europe Conference Exhibition (DATE), pp. 514–519, March 2010