Towards Developing High Performance RISC-V Processors Using Agile Methodology

Author:

Xu Yinan1,Yu Zihao1,Tang Dan1,Chen Guokai1,Chen Lu1,Gou Lingrui1,Jin Yue1,Li Qianruo1,Li Xin1,Li Zuojun1,Lin Jiawei1,Liu Tong1,Liu Zhigang1,Tan Jiazhan1,Wang Huaqiang1,Wang Huizhe1,Wang Kaifan1,Zhang Chuanqi1,Zhang Fawang2,Zhang Linjuan1,Zhang Zifei1,Zhao Yangyang1,Zhou Yaoyang1,Zhou Yike1,Zou Jiangrui2,Cai Ye2,Huan Dandan3,Li Zusong3,Zhao Jiye3,Chen Zihao4,He Wei4,Quan Qiyuan4,Liu Xingwu5,Wang Sa1,Shi Kan1,Sun Ninghui1,Bao Yungang1

Affiliation:

1. Institute of Computing Technology, Chinese Academy of Sciences,State Key Lab of Processors,China

2. Shenzhen University,China

3. Beijing VCore Technology Co., Ltd,China

4. Peng Cheng Laboratory,China

5. Dalian University of Technology,China

Funder

Chinese Academy of Sciences

National Natural Science Foundation of China

Youth Innovation Promotion Association

Publisher

IEEE

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3. Out-of-Order and Recursive RAS: A Return Address Stack Design on High Performance Processor;2024 IEEE 35th International Conference on Application-specific Systems, Architectures and Processors (ASAP);2024-07-24

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