Evaluating and Enhancing Performance through Macro-Op Fusion Optimization with RISC-V

Author:

Shen Jian-Yu1ORCID,Liao Shih-Wei1ORCID

Affiliation:

1. Department of Computer Science & Information Engineering, National Taiwan University, Taiwan

Publisher

ACM

Reference14 articles.

1. [n. d.]. Low Level Virtual Machine. https://github.com/llvm/llvm-project

2. [n. d.]. Quick Emulator. https://github.com/qemu/qemu/tree/stable-8.1

3. [n. d.]. Standard Performance Evaluation Corporation. https://www.spec.org/index.html

4. Brad Calder. [n. d.]. SimPoint: Analyzing the Characteristics of Applications for Dynamic Compilation. https://cseweb.ucsd.edu/ calder/simpoint/index.htm

5. Christopher Celio, Daniel Palmer Dabbelt, David A. Patterson, and Krste Asanovic. 2016. The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V. CoRR abs/1607.02318 (2016). arXiv:1607.02318http://arxiv.org/abs/1607.02318

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