Neural Network Based Design Optimization of 14-nm Node Fully-Depleted SOI FET for SoC and 3DIC applications
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9110268/9117802/09117935.pdf?arnumber=9117935
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Enhancement of ISPP Efficiency Using Neural Network-Based Optimization of 3-D NAND Cell;IEEE Transactions on Electron Devices;2023-07
2. Deep Neural Networks for Determining Subgap States of Oxide Thin-Film Transistors;IEEE Access;2023
3. Efficient modeling approach for simulating multi-physics responses of an ion-sensitive field-effect transistor using artificial neural networks;Journal of Computational Electronics;2022-11-30
4. Bi-Directional Long Short-Term Memory Neural Network Modeling of Data Retention Characterization in 3-D Triple-Level Cell NAND Flash Memory;IEEE Transactions on Electron Devices;2022-08
5. Effect of Temperature on Performance of 5-nm Node Silicon Nanosheet Transistors for Analog Applications;Silicon;2022-03-12
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